1. Field of the Invention
This invention pertains generally to nanoscale fabrication methods, and more particularly to a method of fabricating nanoscale patterns on an electrically configurable layer of a substrate using an electric field mask.
2. Description of Related Art
The progress of lithography in the past three decades has continued to reduce minimum feature size of leading-edge semiconductor devices about 70% with each new generation that is brought forth approximately every two to three years. However, current lithographic techniques face very significant challenges as feature sizes are reduced to nanoscale dimensions. New lithographic solutions have been explored from a number of vantage points, including exposure tools, masks, resists and all the associated processing steps. For example, imprinting lithography has been employed to fabricate nanoscale devices and circuits with high-rates and the capability for being scaled-up to production levels.
However, the industry has not been able to solve the yield and defect problems that arise from the interaction between the mold and the polymer resist during the imprinting lithographic processes. While the use of sequential (non-parallel) beam directed, or pen-based lithographic techniques can not be scaled-up toward mass fabrication.
Accordingly, a need exists for a new nanoscale manufacturing method which provides reliability and practicality while maintaining high-speed and scalability. The present invention fulfills those needs and others while overcoming drawbacks with previous processes.